VIVADO – regular FIFO vs AXI FIFO
Learn what FIFO is and how to use FIFO IP Cores of Vivado Xilinx FPGA tool
What you’ll learn
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Fundamentals of a FIFO
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Differences between regular FIFO to AXI FIFO
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Main uses for FIFOs
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How to read and write a regular FIFO VS AXI FIFO
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How to simulate the FIFOs
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About FIFOs with 2 different clocks for read and write and when should we use it
Requirements
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Basic knowledge of VIVADO is required
Who this course is for:
- Anyone who wants to get familiar with FIFOs uses and implementations
- Anyone who wants to know how transfer data between components with different clocks from each other
- Anyone who wants to know more about VIVADO FIFOs options
