VSD – Distributed timing analysis within 100 lines code

This webinar was conducted on 26th May 2018. 

1) What happens when you type set_multi_cpu_usage -localCpu 4 on your EDA timing shell?
2) What happens when you type set_multi_cpu_usage -localCpu 4 -numThreads 4 on your EDA timing shell?
 
I had a curiosity, while working at my previous design companies, about how jobs are getting spawned on different machines? What if there are less machines and more jobs, and vice versa? How does the algorithm of a timing engine handles this?
 
I myself used to setup the entire distributed MMMC framework for timing tools at customer place, which was just setting the right variables (set_multi_cpu_usage), but never knew what goes behind the tools. Its the curiosity which leads to queries which leads to exploration and finally, leads to
answers. I found my answers from Tsung-Wei, who is the architect of popular opensource STA Tool Opentimer.
 
We all know timing analysis is a really important task in overall chip design flow and its so complex and difficult task. The chip that we incorporate today has billions of transistors, resulting timing analysis runtime is tool large. Also, we need to analyze timing under different conditions, so its not just a single run that you get a final result. While there are several solutions to mitigate this computation issue, the problem is most of the work is architecturally constrained by
single machine. And as design complexity continue to grow larger and larger, we have to add more and more CPU and memories to the machine, but not very cost-efficient
 
There are multiple places, we can introduce distributed computing to timing and major motivation is to speed up the timing closure. We have to analyze timing under different range of conditions, typically quantified as modes (test mode, functional mode) and corner (PVT). The number of combinations (timing views) you have to run is typically increasing exponentially with lower nodes. That’s where you need to need to distribute timing analyses across different machines.
So let’s distribute it and do it within 100lines of code using DTCraft – A High-performance cluster computing engine. Welcome to the webinar on “Distributed timing analysis within 100 lines of code”

Do you want to find your answers too? Enroll in the upcoming webinar on “Distributed timing analysis” with Tsung-Wei, do labs on your own,
understand the framework and I can guarantee you would be a better STA engineer or Lead than you were before

Speaker Profile:Tsung-Wei Huang 

Tsung-Wei Huang is Research Assistant Professor, in Department of Electrical and Computer Engineering at University of Illinois at Urbana-Champaign, IL, USA. He has done his PhD in Electrical and Computer Engineering at UIUC. He holds 2 patents and more than 30 Conference and Journal Paper publications